More titles to consider

Shopping Cart

You're getting the VIP treatment!

With the purchase of Kobo VIP Membership, you're getting 10% off and 2x Kobo Super Points on eligible items.

Item(s) unavailable for purchase
Please review your cart. You can remove the unavailable item(s) now or we'll automatically remove it at Checkout.


Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve real-world design problems.

Contents: Simulation-Based Verification * Introduction to Formal Techniques * Contrasting Simulation vs. Formal Techniques * Developing a Formal Test Plan * Writing High-Level Requirements * Proving High-Level Requirements * System Level Simulation * Design Example * Formal Test Plan * Final System Simulation

Ratings and Reviews

Overall rating

No ratings yet
5 Stars 4 Stars 3 Stars 2 Stars 1 Stars
0 0 0 0 0

Be the first to rate and review this book!

You've already shared your review for this item. Thanks!

We are currently reviewing your submission. Thanks!


You can read this item using any of the following Kobo apps and devices: